﻿                                   YACHT v1.2+
                       (Yet Another Cycle Hunting Table)

This is an unofficial update to v1.2 as permitted by the licensing agreement.


-------------------------------------------------------------------------------
                                   Foreword :
-------------------------------------------------------------------------------
This document is based on :
 - 9th Edition of M68000 8-16-32-bit Microprocessor User's Manual
        (Motorola, 1993) (lately referred to as M68000UM) (*)
 - Programmer's Reference Manual Rev 1
        (Motorola, 1992) (lately referred to as M68000PRM) (*)
   MC68000 16-32-Bit Microprocessor Programming Reference Card Rev 3
        (Motorola, 19xx) (lately referred to as MC68000/AC)
 - US Patent n°4,325,121 - Two level control store for microprogrammed data
 processor (Motorola, Apr, 13, 1982) (lately referred to as USP4325121)
 - Error reports / questions asked by users (see following section)

[* Actually that's just the name of a PDF, not an abbreviated book title.
For my part, I use UM as an abbreviation for the aforementioned user manual.]


-------------------------------------------------------------------------------
                                   Change log :
-------------------------------------------------------------------------------
v1 : intitial release

v1.1 :
- Rewrote parts of the vocabulary section
- Added a "general note" section to this document
- Added a note on Program Counter addressing modes
    - Thanks to Atarizoll & npomarede
    - http://atari-forum.com/viewtopic.php?t=26820
- Added missing BTST Dn,#data timing
    - Thanks to flamewing
    - http://gendev.spritesmind.net/forum/viewtopic.php?t=2917
- Fixed a typo for (xxx).L timing for CLR, NEGX, NEG, NOT
    - Thanks to byuu - http://gendev.spritesmind.net/forum/viewtopic.php?t=3040
- Fixed a copy / paste error for MULU / MULS #data,DN
    - Thanks to TomH - http://www.atari-forum.com/viewtopic.php?t=36648
- Improved the consistency of the exception section
    - Thanks to TomH & ijor - http://www.atari-forum.com/viewtopic.php?t=36648
- Fixed inaccurate exception timings
    - Thanks to ijor - http://www.atari-forum.com/viewtopic.php?t=36648

v1.2 :
- Added references to MC68000/AC as it confirms many guesses (thanks, Bernard)
- Fixed a typo : (d8,An,Xn) instead of (d8,SP,Xn)
- Fixed a typo : (d8,An)    instead of (d8,An,Xn)
- Fixed a copy/paste error for TAS (xxx).W and (xxx).L
    - Thanks to Nemesis - https://www.atari-forum.com/viewtopic.php?p=436402
- Fixed a copy/paste error for ADD/SUB.L for "Dn,<ea>"
    - Thanks to Nemesis - https://www.atari-forum.com/viewtopic.php?p=436402
- Removed tab characters and spaces at the end of lines

v1.2+ (this version) (unofficial update) :
- Fixed a number of obvious errors, mostly read counts and copy/paste errors
- Added a new bus-usage symbol, documented in the Data Bus Usage section
- Rewrote most of the text to improve the grammar, spelling, and clarity
- Removed all references to line numbers
- Added notes and commentary, mostly within [square brackets]
    - All 1.2+ changes originated at https://mijet.eludevisibility.org
    - This file is based on a file from https://github.com/danorf69/YACHT


-------------------------------------------------------------------------------
                                  Vocabulary :
-------------------------------------------------------------------------------
Clock Cycle : time between two adjacent pulses of the oscillator that sets the
tempo of the processor.

Microcycle : (in this document) indivisible CPU cycle of execution lasting two
clock cycles.

Bus Cycle : except for the Read-Modify-Write Cycle that is only used by the TAS
instruction, a bus cycle consists of 8 states (if no wait cycles are needed).
There are 2 bus states per clock cycle so a bus cycle is 4 clock cycles long
(in the best case). Wait states comprise "an integral number of clock cycles".


-------------------------------------------------------------------------------
                                 General note :
-------------------------------------------------------------------------------
This document is primary designed for programmers that need to know exactly
how many clock cycles are used by their code, when memory is read or written,
and in what order. Consequently, the purpose of this document is to correct
and explain the instruction execution times documented in M68000UM.

So, as in section 8 of M68000UM, this document "lists instruction execution
times in terms of external clock (CLK) periods. In this data, it is assumed
that both memory read and write cycles consist of four clock periods. A longer
memory cycle causes the generation of wait states that must be added to the
total instruction times." [You should also consider that Program and Data can
be mapped differently, so the timings may be different. User and Supervisor
function codes can also produce different mappings on some systems.]


-------------------------------------------------------------------------------
                                Rules of thumb :
-------------------------------------------------------------------------------
1) The 68000 external data bus is 16-bit, so any memory operation will take
at least 2 full bus cycles for long words and 1 for words.

2) The 68000 internal data bus is 32-bit, so reading/writing a word or
long word from/to a register takes the same amount time.

3) There are 3 math units. One 16-bit ALU and two 16-bit Address Units. The ALU
was complex enough for the math instruction set while the AUs were only able to
do address related math (addition and subtraction).

So, the ALU is used in the execution of instructions whereas the AUs are used
to calculate the effective address(es). And, of course, the 2 16-bit AUs worked
together to produce 32-bit effective address calculations.

Therefore, for a simple 16-bit math instruction, the ALU can do the operation
while the AUs perform address calculations, all during the same microcycle.

3a) The 68000 ALU is 16-bit so any arithmetic or logic operation involving
long-word values take more cycles than for word values even if the source
and destination are registers.

3b) For arithmetic operations on address registers, such as ADDA and SUBA, the
whole 32-bit destination address register is used regardless of the operation
size (.W or .L). As this arithmetic operation is done by the ALU, not the AUs,
and with regard to the previous rule (3a), the ALU will take longer to perform
word-sized operations on address registers than on data registers.

4a) Generally, the source operand is evaluated first, then the destination
operand is evaluated, and lastly, the instruction is executed. There are
exceptions, however. "ADDI.W #<data>,-(An)", for example, follows this rule.

4b) There are some instructions for which the previous rule doesn't apply,
where the destination operand evaluation starts before the end of the source
operand evaluation. "ABCD.B -(Ay),-(Ax)" is a good example of this rule.

5) SP is an address register (A7) so it follows that (d16,An) and (d16,SP)
have identical timings. Same goes for (d8,An,Xn) and (d8,SP,Xn).

6a) At the start of every instruction, the pipeline always contains two words:
the current instruction opcode and the following word. Unless an exception
occurs, instructions must refill the pipeline ("prefetching") at some point
to replace the word(s) consumed during execution. This explains why most
instructions have at least as many read cycles as the number of words in
the instruction. This behavior is commonly seen when the PC merely advances.

6b) If the pipeline is presumed to no longer be valid then two words must
be fetched in order to refill the pipeline before execution can continue.
This behavior is commonly seen when the PC is changed non-monotonically,
such as after a branch. There are other situations where the pipeline is
treated as invalid, however. The capital-P marker indicates any type of
Program-function-code bus read where the pipeline is assumed to be invalid
(or, in the DBcc case, where it is speculatively invalid).


-------------------------------------------------------------------------------
                              How to read the table :
-------------------------------------------------------------------------------
Exec Time :
-----------
The table use the same rules as M68000UM for the execution times. So the data
is shown as :
            n(r/w)
where:
n is the total number of clock periods
r is the number of read cycles (if any)
w is the number of write cycles (if any).

In addition, each exec time entry is split into two parts (when possible) :
"instruction exec time" and "effective address exec time". The two exec times
must be added in order to get the total exec time.

Data Bus Usage :
----------------
Each character below describes the state of the data bus during a microcycle.
n  : nop; the data bus is not used by the CPU
n- : nop with idle wait; no transfers occur during this microcycle
     (can last two microcycles instead of one?) [I don't understand this one.]
p  : Program fetch; read from the next consecutive location in program memory
P  : Same as 'p' but with semantics of refilling a potentially invalid pipeline
W  : Write MSW of a long word to the data bus
w  : Write one word to the data bus (LSW for long-word operations)
R  : Read MSW of a long word from the data bus
r  : Read one word from the data bus (LSW for long-word operations)
S  : Push (write) MSW of a long word to the stack             ['S' for Stack]
s  : Push (write) one word to the stack (LSW for long-word operations)
U  : Pop (read) MSW of a long word from the stack             ['U' for Unstack]
u  : Pop (read) one word from the stack (LSW for long-word operations)
V  : Fetch vector MSW (for exceptions)
v  : Fetch vector LSW (for exceptions)
i  : Vector number acquisition in an IACK Cycle (for Interrupt exception)
F  : Fetch SSP MSW (for /RESET exception)
f  : Fetch SSP LSW (for /RESET exception)

Spacing (or lack thereof) and vertical bars (|) are for ease of reading only.

Examples :
----------

Note : in the following examples, 'n' will be replaced by '.' for clarity.

1) MOVE.W -(An),Dn :
Takes 10 clock cycles (data bus read 2 times, written 0 times)
Data bus usage : ..r.p

2) EORI.L #<data>,-(An) :
Takes 30 clock cycles (data bus read 5 times, written 2 times)
Data bus usage : .p.p..R.r.p.w.W

Note on Program Counter addressing modes :
------------------------------------------
(d16,PC) and (d16,An) always(*) behave the same. It's also true for (d8,PC,Xn)
and (d8,An,Xn). So if you want to know the exact timing of an instruction with
PC related effective address, once you've ensured that the addressing mode is
valid for the instruction, please refer to the corresponding An line.

[* Not always true. PC modes use Program; An modes use Data. The base timings
should be identical, however, so there is no need to list them separately.]




*******************************************************************************
                   OPERAND EFFECTIVE ADDRESS CALCULATION TIMES
*******************************************************************************
-------------------------------------------------------------------------------
       <ea>       |    Exec Time    |               Data Bus Usage
------------------+-----------------+------------------------------------------
.B or .W :        |                 |
  Dn              |          0(0/0) |
  An              |          0(0/0) |
  (An)            |          4(1/0) |                              nr
  (An)+           |          4(1/0) |                              nr
  -(An)           |          6(1/0) |                   n          nr
  (d16,An)        |          8(2/0) |                        np    nr
  (d8,An,Xn)      |         10(2/0) |                   n    np    nr
  (xxx).W         |          8(2/0) |                        np    nr
  (xxx).L         |         12(3/0) |                     np np    nr
  #<data>         |          4(1/0) |                        np
.L :              |                 |
  Dn              |          0(0/0) |
  An              |          0(0/0) |
  (An)            |          8(2/0) |                           nR nr
  (An)+           |          8(2/0) |                           nR nr
  -(An)           |         10(2/0) |                   n       nR nr
  (d16,An)        |         12(3/0) |                        np nR nr
  (d8,An,Xn)      |         14(3/0) |                   n    np nR nr
  (xxx).W         |         12(3/0) |                        np nR nr
  (xxx).L         |         16(4/0) |                     np np nR nr
  #<data>         |          8(2/0) |                     np np




*******************************************************************************
  Line 0000 :
    ADDI, ANDI, ANDI to CCR, BCHG, BCLR, BSET, BTST, CMPI, EORI, EORI to CCR,
    MOVEP, ORI, ORI to CCR, SUBI
*******************************************************************************

-------------------------------------------------------------------------------
 EORI, ORI, ANDI, |    Exec Time    |               Data Bus Usage
    SUBI, ADDI    | INSTR+Op1  EA   | 1st Operand |  2nd OP (ea)  |   INSTR
------------------+-----------------+-------------+---------------+------------
#<data>,<ea> :    |                 |             |               |
  .B or .W :      |                 |             |               |
    Dn            |  8(2/0)  0(0/0) |          np |               | np
    (An)          | 12(2/1)  4(1/0) |          np |            nr | np nw
    (An)+         | 12(2/1)  4(1/0) |          np |            nr | np nw
    -(An)         | 12(2/1)  6(1/0) |          np | n          nr | np nw
    (d16,An)      | 12(2/1)  8(2/0) |          np |      np    nr | np nw
    (d8,An,Xn)    | 12(2/1) 10(2/0) |          np | n    np    nr | np nw
    (xxx).W       | 12(2/1)  8(2/0) |          np |      np    nr | np nw
    (xxx).L       | 12(2/1) 12(3/0) |          np |   np np    nr | np nw
  .L :                              |             |               |
    Dn            | 16(3/0)  0(0/0) |       np np |               | np       nn
    (An)          | 20(3/2)  8(2/0) |       np np |         nR nr | np nw nW
    (An)+         | 20(3/2)  8(2/0) |       np np |         nR nr | np nw nW
    -(An)         | 20(3/2) 10(2/0) |       np np | n       nR nr | np nw nW
    (d16,An)      | 20(3/2) 12(3/0) |       np np |      np nR nr | np nw nW
    (d8,An,Xn)    | 20(3/2) 14(3/0) |       np np | n    np nR nr | np nw nW
    (xxx).W       | 20(3/2) 12(3/0) |       np np |      np nR nr | np nw nW
    (xxx).L       | 20(3/2) 16(4/0) |       np np |   np np nR nr | np nw nW
NOTES :
  .M68000UM probably has the wrong instruction timing for the ANDI.L #<data>,Dn
   instruction. It reads "14(3/0)" but, according to USP4325121, this
   instruction is based on the same microwords as EORI.L #<data>,Dn and
   ORI.L #<data>,Dn which have a "16(3/0)" timing. In addition, evaluations
   on real hardware, as well as MC68000/AC, confirm the 16-cycle timing.

-------------------------------------------------------------------------------
 ORI, ANDI, EORI  |    Exec Time    |               Data Bus Usage
  to CCR, to SR   |      INSTR      | 1st Operand |          INSTR
------------------+-----------------+-------------+----------------------------
#<data>,CCR       |                 |             |
  .B :            | 20(3/0)         |          np |              nn nn nP nP

NOTE:
 The reason the pipeline is invalidated is because the S bit may have changed.
 This still occurs even when S can't be changed, such as the "to CCR" cases.

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       CMPI       |  INSTR     EA   | 1st Operand |  2nd OP (ea)  |   INSTR
------------------+-----------------+-------------+-------------+--------------
#<data>,<ea> :    |                 |             |               |
  .B or .W :      |                 |             |               |
    Dn            |  8(2/0)  0(0/0) |          np |               | np
    (An)          |  8(2/0)  4(1/0) |          np |            nr | np
    (An)+         |  8(2/0)  4(1/0) |          np |            nr | np
    -(An)         |  8(2/0)  6(1/0) |          np | n          nr | np
    (d16,An)      |  8(2/0)  8(2/0) |          np |      np    nr | np
    (d8,An,Xn)    |  8(2/0) 10(2/0) |          np | n    np    nr | np
    (xxx).W       |  8(2/0)  8(2/0) |          np |      np    nr | np
    (xxx).L       |  8(2/0) 12(3/0) |          np |   np np    nr | np
  .L :            |                 |             |               |
    Dn            | 14(3/0)  0(0/0) |       np np |               | np       n
    (An)          | 12(3/0)  8(2/0) |       np np |         nR nr | np
    (An)+         | 12(3/0)  8(2/0) |       np np |         nR nr | np
    -(An)         | 12(3/0) 10(2/0) |       np np | n       nR nr | np
    (d16,An)      | 12(3/0) 12(3/0) |       np np |      np nR nr | np
    (d8,An,Xn)    | 12(3/0) 14(3/0) |       np np | n    np nR nr | np
    (xxx).W       | 12(3/0) 12(3/0) |       np np |      np nR nr | np
    (xxx).L       | 12(3/0) 16(4/0) |       np np |   np np nR nr | np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
    BCHG, BSET    |  INSTR     EA   | 1st Operand |  2nd OP (ea)  |      INSTR
------------------+-----------------+-------------+---------------+------------
Dn,<ea> :         |                 |             |               |
  .B :            |                 |             |               |
    (An)          |  8(1/1)  4(1/0) |             |            nr | np    nw
    (An)+         |  8(1/1)  4(1/0) |             |            nr | np    nw
    -(An)         |  8(1/1)  6(1/0) |             | n          nr | np    nw
    (d16,An)      |  8(1/1)  8(2/0) |             |      np    nr | np    nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) |             | n    np    nr | np    nw
    (xxx).W       |  8(1/1)  8(2/0) |             |      np    nr | np    nw
    (xxx).L       |  8(1/1) 12(3/0) |             |   np np    nr | np    nw
Dn,Dm :           |                 |             |               |
  .L :            |                 |             |               |
    if Dn<16      |  6(1/0)  0(0/0) |             |               | np       n
    if Dn>15      |  8(1/0)  0(0/0) |             |               | np       nn
#<data>,<ea> :    |                 |             |               |
  .B :            |                 |             |               |
    (An)          | 12(2/1)  4(1/0) |          np |            nr | np    nw
    (An)+         | 12(2/1)  4(1/0) |          np |            nr | np    nw
    -(An)         | 12(2/1)  6(1/0) |          np | n          nr | np    nw
    (d16,An)      | 12(2/1)  8(2/0) |          np |      np    nr | np    nw
    (d8,An,Xn)    | 12(2/1) 10(2/0) |          np | n    np    nr | np    nw
    (xxx).W       | 12(2/1)  8(2/0) |          np |      np    nr | np    nw
    (xxx).L       | 12(2/1) 12(3/0) |          np |   np np    nr | np    nw
#<data>,Dn :      |                 |             |               |
  .L :            |                 |             |               |
    if data<16    | 10(2/0)  0(0/0) |          np |               | np       n
    if data>15    | 12(2/0)  0(0/0) |          np |               | np       nn

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       BCLR       |  INSTR     EA   | 1st Operand |  2nd OP (ea)  |   INSTR
------------------+-----------------+-------------+---------------+------------
Dn,<ea> :         |                 |             |               |
  .B :            |                 |             |               |
    (An)          |  8(1/1)  4(1/0) |             |            nr | np    nw
    (An)+         |  8(1/1)  4(1/0) |             |            nr | np    nw
    -(An)         |  8(1/1)  6(1/0) |             | n          nr | np    nw
    (d16,An)      |  8(1/1)  8(2/0) |             |      np    nr | np    nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) |             | n    np    nr | np    nw
    (xxx).W       |  8(1/1)  8(2/0) |             |      np    nr | np    nw
    (xxx).L       |  8(1/1) 12(3/0) |             |   np np    nr | np    nw
Dn,Dm :           |                 |             |               |
  .L :            |                 |             |               |
    if Dn<16      |  8(1/0)  0(0/0) |             |               | np nn
    if Dn>15      | 10(1/0)  0(0/0) |             |               | np nn n
#<data>,<ea> :    |                 |             |               |
  .B :            |                 |             |               |
    (An)          | 12(2/1)  4(1/0) |          np |            nr | np    nw
    (An)+         | 12(2/1)  4(1/0) |          np |            nr | np    nw
    -(An)         | 12(2/1)  6(1/0) |          np | n          nr | np    nw
    (d16,An)      | 12(2/1)  8(2/0) |          np |      np    nr | np    nw
    (d8,An,Xn)    | 12(2/1) 10(2/0) |          np | n    np    nr | np    nw
    (xxx).W       | 12(2/1)  8(2/0) |          np |      np    nr | np    nw
    (xxx).L       | 12(2/1) 12(3/0) |          np |   np np    nr | np    nw
#<data>,Dn :      |                 |             |               |
  .L :            |                 |             |               |
    if data<16    | 12(2/0)  0(0/0) |          np |               | np nn
    if data>15    | 14(2/0)  0(0/0) |          np |               | np nn n

[BCLR is indeed slower than the other instructions, according to the UM.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       BTST       |  INSTR     EA   | 1st Operand |  2nd OP (ea)  |   INSTR
------------------+-----------------+-------------+---------------+------------
Dn,<ea> :         |                 |             |               |
  .B :            |                 |             |               |
    (An)          |  4(1/0)  4(1/0) |             |            nr | np
    (An)+         |  4(1/0)  4(1/0) |             |            nr | np
    -(An)         |  4(1/0)  6(1/0) |             | n          nr | np
    (d16,An)      |  4(1/0)  8(2/0) |             |      np    nr | np
    (d8,An,Xn)    |  4(1/0) 10(2/0) |             | n    np    nr | np
    (xxx).W       |  4(1/0)  8(2/0) |             |      np    nr | np
    (xxx).L       |  4(1/0) 12(3/0) |             |   np np    nr | np
    #<data>       |  6(1/0)  4(1/0) |             |      np       | np n
Dn,Dm :           |                 |             |               |
  .L :            |  6(1/0)  0(0/0) |             |               | np n
#<data>,<ea> :    |                 |             |               |
  .B :            |                 |             |               |
    (An)          |  8(2/0)  4(1/0) |          np |            nr | np
    (An)+         |  8(2/0)  4(1/0) |          np |            nr | np
    -(An)         |  8(2/0)  6(1/0) |          np | n          nr | np
    (d16,An)      |  8(2/0)  8(2/0) |          np |      np    nr | np
    (d8,An,Xn)    |  8(2/0) 10(2/0) |          np | n    np    nr | np
    (xxx).W       |  8(2/0)  8(2/0) |          np |      np    nr | np
    (xxx).L       |  8(2/0) 12(3/0) |          np |   np np    nr | np
#<data>,Dn :      |                 |             |               |
  .L :            | 10(2/0)  0(0/0) |          np |               | np n

[UM tables lack an asterisk for BTST implying that the timing is consistent.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
      MOVEP       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
Dx,(d16,Ay) :     |                 |
  .W :            | 16(2/2)         |                np    nW    nw np
  .L :            | 24(2/4)         |                np nW nW nw nw np
(d16,Ay),Dx :     |                 |
  .W :            | 16(4/0)         |                np    nR    nr np
  .L :            | 24(6/0)         |                np nR nR nr nr np
NOTES :
  .Read and write operations are done from the MSB to the LSB on 2 words if
  using ".w" (first read/write word at Ay+d16 then word at Ay+d16+2), and on
  4 words if using ".l" (first read/write word at Ay+d16 then word at Ay+d16+2
  then word at Ay+d16+4 and finally word at Ay+d16+6).




*******************************************************************************
  Line 0001         &          Line 0010          &          Line 0011
    MOVE.B                       MOVE.L, MOVEA.L               MOVE.W, MOVEA.W
*******************************************************************************

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       MOVE       |      INSTR      |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,Dn :         |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)         |               |               np
    An            |  4(1/0)         |               |               np
    (An)          |  8(2/0)         |            nr |               np
    (An)+         |  8(2/0)         |            nr |               np
    -(An)         | 10(2/0)         | n          nr |               np
    (d16,An)      | 12(3/0)         |      np    nr |               np
    (d8,An,Xn)    | 14(3/0)         | n    np    nr |               np
    (xxx).W       | 12(3/0)         |      np    nr |               np
    (xxx).L       | 16(4/0)         |   np np    nr |               np
    #<data>       |  8(2/0)         |      np       |               np
  .L :            |                 |               |
    Dn            |  4(1/0)         |               |               np
    An            |  4(1/0)         |               |               np
    (An)          | 12(3/0)         |         nR nr |               np
    (An)+         | 12(3/0)         |         nR nr |               np
    -(An)         | 14(3/0)         | n       nR nr |               np
    (d16,An)      | 16(4/0)         |      np nR nr |               np
    (d8,An,Xn)    | 18(4/0)         | n    np nR nr |               np
    (xxx).W       | 16(4/0)         |      np nR nr |               np
    (xxx).L       | 20(5/0)         |   np np nR nr |               np
    #<data>       | 12(3/0)         |   np np       |               np
<ea>,(An) :       |                 |               |
  .B or .W :      |                 |               |
    Dn            |  8(1/1)         |               |            nw np
    An            |  8(1/1)         |               |            nw np
    (An)          | 12(2/1)         |            nr |            nw np
    (An)+         | 12(2/1)         |            nr |            nw np
    -(An)         | 14(2/1)         | n          nr |            nw np
    (d16,An)      | 16(3/1)         |      np    nr |            nw np
    (d8,An,Xn)    | 18(3/1)         | n    np    nr |            nw np
    (xxx).W       | 16(3/1)         |      np    nr |            nw np
    (xxx).L       | 20(4/1)         |   np np    nr |            nw np
    #<data>       | 12(2/1)         |      np       |            nw np
  .L :            |                 |               |
    Dn            | 12(1/2)         |               |         nW nw np
    An            | 12(1/2)         |               |         nW nw np
    (An)          | 20(3/2)         |         nR nr |         nW nw np
    (An)+         | 20(3/2)         |         nR nr |         nW nw np
    -(An)         | 22(3/2)         | n       nR nr |         nW nw np
    (d16,An)      | 24(4/2)         |      np nR nr |         nW nw np
    (d8,An,Xn)    | 26(4/2)         | n    np nR nr |         nW nw np
    (xxx).W       | 24(4/2)         |      np nR nr |         nW nw np
    (xxx).L       | 28(5/2)         |   np np nR nr |         nW nw np
    #<data>       | 20(3/2)         |   np np       |         nW nw np
<ea>,(An)+ :      |                 |               |
  .B or .W :      |                 |               |
    Dn            |  8(1/1)         |               |            nw np
    An            |  8(1/1)         |               |            nw np
    (An)          | 12(2/1)         |            nr |            nw np
    (An)+         | 12(2/1)         |            nr |            nw np
    -(An)         | 14(2/1)         | n          nr |            nw np
    (d16,An)      | 16(3/1)         |      np    nr |            nw np
    (d8,An,Xn)    | 18(3/1)         | n    np    nr |            nw np
    (xxx).W       | 16(3/1)         |      np    nr |            nw np
    (xxx).L       | 20(4/1)         |   np np    nr |            nw np
    #<data>       | 12(2/1)         |      np       |            nw np
  .L :            |                 |               |
    Dn            | 12(1/2)         |               |         nW nw np
    An            | 12(1/2)         |               |         nW nw np
    (An)          | 20(3/2)         |         nR nr |         nW nw np
    (An)+         | 20(3/2)         |         nR nr |         nW nw np
    -(An)         | 22(3/2)         | n       nR nr |         nW nw np
    (d16,An)      | 24(4/2)         |      np nR nr |         nW nw np
    (d8,An,Xn)    | 26(4/2)         | n    np nR nr |         nW nw np
    (xxx).W       | 24(4/2)         |      np nR nr |         nW nw np
    (xxx).L       | 28(5/2)         |   np np nR nr |         nW nw np
    #<data>       | 20(3/2)         |   np np       |         nW nw np
<ea>,-(An) :      |                 |               |
  .B or .W :      |                 |               |
    Dn            |  8(1/1)         |               |                  np nw
    An            |  8(1/1)         |               |                  np nw
    (An)          | 12(2/1)         |            nr |                  np nw
    (An)+         | 12(2/1)         |            nr |                  np nw
    -(An)         | 14(2/1)         | n          nr |                  np nw
    (d16,An)      | 16(3/1)         |      np    nr |                  np nw
    (d8,An,Xn)    | 18(3/1)         | n    np    nr |                  np nw
    (xxx).W       | 16(3/1)         |      np    nr |                  np nw
    (xxx).L       | 20(4/1)         |   np np    nr |                  np nw
    #<data>       | 12(2/1)         |      np       |                  np nw
  .L :            |                 |               |
    Dn            | 12(1/2)         |               |                  np nw nW
    An            | 12(1/2)         |               |                  np nw nW
    (An)          | 20(3/2)         |         nR nr |                  np nw nW
    (An)+         | 20(3/2)         |         nR nr |                  np nw nW
    -(An)         | 22(3/2)         | n       nR nr |                  np nw nW
    (d16,An)      | 24(4/2)         |      np nR nr |                  np nw nW
    (d8,An,Xn)    | 26(4/2)         | n    np nR nr |                  np nw nW
    (xxx).W       | 24(4/2)         |      np nR nr |                  np nw nW
    (xxx).L       | 28(5/2)         |   np np nR nr |                  np nw nW
    #<data>       | 20(3/2)         |   np np       |                  np nw nW
<ea>,(d16,An) :   |                 |               |
  .B or .W :      |                 |               |
    Dn            | 12(2/1)         |               |      np    nw np
    An            | 12(2/1)         |               |      np    nw np
    (An)          | 16(3/1)         |            nr |      np    nw np
    (An)+         | 16(3/1)         |            nr |      np    nw np
    -(An)         | 18(3/1)         | n          nr |      np    nw np
    (d16,An)      | 20(4/1)         |      np    nr |      np    nw np
    (d8,An,Xn)    | 22(4/1)         | n    np    nr |      np    nw np
    (xxx).W       | 20(4/1)         |      np    nr |      np    nw np
    (xxx).L       | 24(5/1)         |   np np    nr |      np    nw np
    #<data>       | 16(3/1)         |      np       |      np    nw np
  .L :            |                 |               |
    Dn            | 16(2/2)         |               |      np nW nw np
    An            | 16(2/2)         |               |      np nW nw np
    (An)          | 24(4/2)         |         nR nr |      np nW nw np
    (An)+         | 24(4/2)         |         nR nr |      np nW nw np
    -(An)         | 26(4/2)         | n       nR nr |      np nW nw np
    (d16,An)      | 28(5/2)         |      np nR nr |      np nW nw np
    (d8,An,Xn)    | 30(5/2)         | n    np nR nr |      np nW nw np
    (xxx).W       | 28(5/2)         |      np nR nr |      np nW nw np
    (xxx).L       | 32(6/2)         |   np np nR nr |      np nW nw np
    #<data>       | 24(4/2)         |   np np       |      np nW nw np
<ea>,(d8,An,Xn) : |                 |               |
  .B or .W :      |                 |               |
    Dn            | 14(2/1)         |               | n    np    nw np
    An            | 14(2/1)         |               | n    np    nw np
    (An)          | 18(3/1)         |            nr | n    np    nw np
    (An)+         | 18(3/1)         |            nr | n    np    nw np
    -(An)         | 20(3/1)         | n          nr | n    np    nw np
    (d16,An)      | 22(4/1)         |      np    nr | n    np    nw np
    (d8,An,Xn)    | 24(4/1)         | n    np    nr | n    np    nw np
    (xxx).W       | 22(4/1)         |      np    nr | n    np    nw np
    (xxx).L       | 26(5/1)         |   np np    nr | n    np    nw np
    #<data>       | 18(3/1)         |      np       | n    np    nw np
  .L :            |                 |               |
    Dn            | 18(2/2)         |               | n    np nW nw np
    An            | 18(2/2)         |               | n    np nW nw np
    (An)          | 26(4/2)         |         nR nr | n    np nW nw np
    (An)+         | 26(4/2)         |         nR nr | n    np nW nw np
    -(An)         | 28(4/2)         | n       nR nr | n    np nW nw np
    (d16,An)      | 30(5/2)         |      np nR nr | n    np nW nw np
    (d8,An,Xn)    | 32(5/2)         | n    np nR nr | n    np nW nw np
    (xxx).W       | 30(5/2)         |      np nR nr | n    np nW nw np
    (xxx).L       | 34(6/2)         |   np np nR nr | n    np nW nw np
    #<data>       | 26(4/2)         |   np np       | n    np nW nw np
<ea>,(xxx).W :    |                 |               |
  .B or .W :      |                 |               |
    Dn            | 12(2/1)         |               |      np    nw np
    An            | 12(2/1)         |               |      np    nw np
    (An)          | 16(3/1)         |            nr |      np    nw np
    (An)+         | 16(3/1)         |            nr |      np    nw np
    -(An)         | 18(3/1)         | n          nr |      np    nw np
    (d16,An)      | 20(4/1)         |      np    nr |      np    nw np
    (d8,An,Xn)    | 22(4/1)         | n    np    nr |      np    nw np
    (xxx).W       | 20(4/1)         |      np    nr |      np    nw np
    (xxx).L       | 24(5/1)         |   np np    nr |      np    nw np
    #<data>       | 16(3/1)         |      np       |      np    nw np
  .L :            |                 |               |
    Dn            | 16(2/2)         |               |      np nW nw np
    An            | 16(2/2)         |               |      np nW nw np
    (An)          | 24(4/2)         |         nR nr |      np nW nw np
    (An)+         | 24(4/2)         |         nR nr |      np nW nw np
    -(An)         | 26(4/2)         | n       nR nr |      np nW nw np
    (d16,An)      | 28(5/2)         |      np nR nr |      np nW nw np
    (d8,An,Xn)    | 30(5/2)         | n    np nR nr |      np nW nw np
    (xxx).W       | 28(5/2)         |      np nR nr |      np nW nw np
    (xxx).L       | 32(6/2)         |   np np nR nr |      np nW nw np
    #<data>       | 24(4/2)         |   np np       |      np nW nw np
<ea>,(xxx).L :    |                 |               |
  .B or .W :      |                 |               |
    Dn            | 16(3/1)         |               |   np np    nw np
    An            | 16(3/1)         |               |   np np    nw np
    (An)          | 20(4/1)         |            nr |      np    nw np np
    (An)+         | 20(4/1)         |            nr |      np    nw np np
    -(An)         | 22(4/1)         | n          nr |      np    nw np np
    (d16,An)      | 24(5/1)         |      np    nr |      np    nw np np
    (d8,An,Xn)    | 26(5/1)         | n    np    nr |      np    nw np np
    (xxx).W       | 24(5/1)         |      np    nr |      np    nw np np
    (xxx).L       | 28(6/1)         |   np np    nr |      np    nw np np
    #<data>       | 20(4/1)         |      np       |   np np    nw np
  .L :            |                 |               |
    Dn            | 20(3/2)         |               |   np np nW nw np
    An            | 20(3/2)         |               |   np np nW nw np
    (An)          | 28(5/2)         |         nR nr |      np nW nw np np
    (An)+         | 28(5/2)         |         nR nr |      np nW nw np np
    -(An)         | 30(5/2)         | n       nR nr |      np nW nw np np
    (d16,An)      | 32(6/2)         |      np nR nr |      np nW nw np np
    (d8,An,Xn)    | 34(6/2)         | n    np nR nr |      np nW nw np np
    (xxx).W       | 32(6/2)         |      np nR nr |      np nW nw np np
    (xxx).L       | 36(7/2)         |   np np nR nr |      np nW nw np np
    #<data>       | 28(5/2)         |   np np       |   np np nW nw np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
      MOVEA       |      INSTR      |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,An :         |                 |               |
  .W :            |                 |               |
    Dn            |  4(1/0)         |               |               np
    An            |  4(1/0)         |               |               np
    (An)          |  8(2/0)         |            nr |               np
    (An)+         |  8(2/0)         |            nr |               np
    -(An)         | 10(2/0)         | n          nr |               np
    (d16,An)      | 12(3/0)         |      np    nr |               np
    (d8,An,Xn)    | 14(3/0)         | n    np    nr |               np
    (xxx).W       | 12(3/0)         |      np    nr |               np
    (xxx).L       | 16(4/0)         |   np np    nr |               np
    #<data>       |  8(2/0)         |      np       |               np
  .L :            |                 |               |
    Dn            |  4(1/0)         |               |               np
    An            |  4(1/0)         |               |               np
    (An)          | 12(3/0)         |         nR nr |               np
    (An)+         | 12(3/0)         |         nR nr |               np
    -(An)         | 14(3/0)         | n       nR nr |               np
    (d16,An)      | 16(4/0)         |      np nR nr |               np
    (d8,An,Xn)    | 18(4/0)         | n    np nR nr |               np
    (xxx).W       | 16(4/0)         |      np nR nr |               np
    (xxx).L       | 20(5/0)         |   np np nR nr |               np
    #<data>       | 12(3/0)         |   np np       |               np




*******************************************************************************
  Line 0100
    CHK, CLR, EXT, ILLEGAL, JMP, JSR, LEA , LINK, MV fr/to CCR/SR, MOVEM, NBCD,
    NEG, NEGX, NOP, NOT, PEA, RTR, RTS, SWAP, STOP, TAS, TRAP, TRAPV, TST, UNLK
*******************************************************************************

-------------------------------------------------------------------------------
        CLR,      |    Exec Time    |               Data Bus Usage
  NEGX, NEG, NOT  |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea> :            |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    (An)          |  8(1/1)  4(1/0) |            nr |               np nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np nw
  .L :            |                 |               |
    Dn            |  6(1/0)  0(0/0) |               |               np       n
    (An)          | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    (An)+         | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    -(An)         | 12(1/2) 10(2/0) | n       nR nr |               np nw nW
    (d16,An)      | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (d8,An,Xn)    | 12(1/2) 14(3/0) | n    np nR nr |               np nw nW
    (xxx).W       | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (xxx).L       | 12(1/2) 16(4/0) |   np np nR nr |               np nw nW

-------------------------------------------------------------------------------
       MOVE       |    Exec Time    |               Data Bus Usage
     from SR      |  INSTR     EA   |  2nd Op (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
SR,<ea> :         |                 |               |
  .W :            |                 |               |
    Dn            |  6(1/0)  0(0/0) |               |               np       n
    (An)          |  8(1/1)  4(1/0) |            nr |               np nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np nw

-------------------------------------------------------------------------------
       MOVE       |    Exec Time    |               Data Bus Usage
  to CCR, to SR   |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,CCR :        |                 |               |
  .W :            |                 |               |
    Dn            | 12(2/0)  0(0/0) |               |         nn nP nP
    (An)          | 12(2/0)  4(1/0) |            nr |         nn nP nP
    (An)+         | 12(2/0)  4(1/0) |            nr |         nn nP nP
    -(An)         | 12(2/0)  6(1/0) | n          nr |         nn nP nP
    (d16,An)      | 12(2/0)  8(2/0) |      np    nr |         nn nP nP
    (d8,An,Xn)    | 12(2/0) 10(2/0) | n    np    nr |         nn nP nP
    (xxx).W       | 12(2/0)  8(2/0) |      np    nr |         nn nP nP
    (xxx).L       | 12(2/0) 12(3/0) |   np np    nr |         nn nP nP
    #<data>       | 12(2/0)  4(1/0) |      np       |         nn nP nP
NOTE:
 The UM says 12(1/0) for "to CCR" which is probably wrong. See the '008 table.

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       NBCD       |      INSTR      |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea> :            |                 |               |
  .B :            |                 |               |
    Dn            |  6(1/0)  0(0/0) |               |               np       n
    (An)          |  8(1/1)  4(1/0) |            nr |               np nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np nw

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        PEA       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
<ea> :            |                 |
  .L :            |                 |
    (An)          | 12(1/2)         |                               np nS ns
    (d16,An)      | 16(2/2)         |                          np   np nS ns
    (d8,An,Xn)    | 20(2/2)         |                        n np n np nS ns
    (xxx).W       | 16(2/2)         |                               np nS ns np
    (xxx).L       | 20(3/2)         |                          np   np nS ns np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       SWAP       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
Dn :              |                 |
  .W :            |  4(1/0)         |                               np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
      MOVEM       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
M --> R           |                 |
  .W              |                 |
    (An)          | 12+4m(3+m/0)    |                np (nr)*    nr np
    (An)+         | 12+4m(3+m/0)    |                np (nr)*    nr np
    (d16,An)      | 16+4m(4+m/0)    |             np np (nr)*    nr np
    (d8,An,Xn)    | 18+4m(4+m/0)    |          np n  np (nr)*    nr np
    (xxx).W       | 16+4m(4+m/0)    |             np np (nr)*    nr np
    (xxx).L       | 20+4m(5+m/0)    |          np np np (nr)*    nr np
  .L              |                 |
    (An)          | 12+8m(3+2m/0)   |                np nR (nr nR)* np
    (An)+         | 12+8m(3+2m/0)   |                np nR (nr nR)* np
    (d16,An)      | 16+8m(4+2m/0)   |             np np nR (nr nR)* np
    (d8,An,Xn)    | 18+8m(4+2m/0)   |          np n  np nR (nr nR)* np
    (xxx).W       | 16+8m(4+2m/0)   |             np np nR (nr nR)* np
    (xxx).L       | 20+8m(5+2m/0)   |          np np np nR (nr nR)* np
R --> M           |                 |
  .W              |                 |
    (An)          |  8+4m(2/m)      |                np (nw)*       np
    -(An)         |  8+4m(2/m)      |                np (nw)*       np
    (d16,An)      | 12+4m(3/m)      |             np np (nw)*       np
    (d8,An,Xn)    | 14+4m(3/m)      |          np n  np (nw)*       np
    (xxx).W       | 12+4m(3/m)      |             np np (nw)*       np
    (xxx).L       | 16+4m(4/m)      |          np np np (nw)*       np
  .L              |                 |
    (An)          |  8+8m(2/2m)     |                np (nW nw)*    np
    -(An)         |  8+8m(2/2m)     |                np (nw nW)*    np
    (d16,An)      | 12+8m(3/2m)     |             np np (nW nw)*    np
    (d8,An,Xn)    | 14+8m(3/2m)     |          np n  np (nW nw)*    np
    (xxx).W       | 12+8m(3/2m)     |             np np (nW nw)*    np
    (xxx).L       | 16+8m(4/2m)     |          np np np (nW nw)*    np
NOTES :
  .'m' is the number of registers to move.
  .'(nr)*' should be replaced by m consecutive 'nr'
  .'(nw)*' should be replaced by m consecutive 'nw'
  .'(nR nr)*' should be replaced by m consecutive 'nR nr'
  .'(nW nw)*' (or '(nw nW)*') should be replaced by m consecutive 'nW nw' (or m
   consecutive 'nw nW').
  .In M --> R mode, an extra bus read cycle occurs. This extra access can cause
   errors (for example, if reading beyond the bounds of physical memory).
  .In M --> R mode, MOVEM.W sign-extends words moved to data registers.

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        EXT       |      INSTR      |  1st Operand  |          INSTR
------------------+-----------------+---------------+--------------------------
Dn :              |                 |               |
  .W :            |  4(1/0)         |               |               np
  .L :            |  4(1/0)         |               |               np

-------------------------------------------------------------------------------
                  |     Exec Time   |               Data Bus Usage
       TST        |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea> :            |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    (An)          |  4(1/0)  4(1/0) |            nr |               np
    (An)+         |  4(1/0)  4(1/0) |            nr |               np
    -(An)         |  4(1/0)  6(1/0) | n          nr |               np
    (d16,An)      |  4(1/0)  8(2/0) |      np    nr |               np
    (d8,An,Xn)    |  4(1/0) 10(2/0) | n    np    nr |               np
    (xxx).W       |  4(1/0)  8(2/0) |      np    nr |               np
    (xxx).L       |  4(1/0) 12(3/0) |   np np    nr |               np
  .L              |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    (An)          |  4(1/0)  8(2/0) |         nR nr |               np
    (An)+         |  4(1/0)  8(2/0) |         nR nr |               np
    -(An)         |  4(1/0) 10(2/0) | n       nR nr |               np
    (d16,An)      |  4(1/0) 12(3/0) |      np nR nr |               np
    (d8,An,Xn)    |  4(1/0) 14(3/0) | n    np nR nr |               np
    (xxx).W       |  4(1/0) 12(3/0) |      np nR nr |               np
    (xxx).L       |  4(1/0) 16(4/0) |   np np nR nr |               np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       TAS        |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea> :            |                 |               |
  .B :            |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    (An)          | 10(1/1)  4(1/0) |            nr |          n nw np
    (An)+         | 10(1/1)  4(1/0) |            nr |          n nw np
    -(An)         | 10(1/1)  6(1/0) | n          nr |          n nw np
    (d16,An)      | 10(1/1)  8(2/0) |      np    nr |          n nw np
    (d8,An,Xn)    | 10(1/1) 10(2/0) | n    np    nr |          n nw np
    (xxx).W       | 10(1/1)  8(2/0) |      np    nr |          n nw np
    (xxx).L       | 10(1/1) 12(3/0) |   np np    nr |          n nw np
NOTES :
  .M68000UM is probably wrong about the instruction timing for memory modes.
   It reads "14(2/1)" but according to the same book, the read-modify-write
   bus cycle used by this instruction is only 10 clock cycles long which
   seems congruent with the microword decomposition in USP4325121. Lastly,
   MC68000/AC and evaluation on real hardware confirm the 10-cycle timing.
  .On many systems, TAS on memory is not safe to use.

-------------------------------------------------------------------------------
              |   Exec Time    |               Data Bus Usage
        CHK   |  INSTR    EA   |  1st OP (ea)  |          INSTR
--------------+----------------+---------------+-------------------------------
no trap :     |                |              /
 <ea>,Dn :    |                |             /
  .W :        |                |            /
   Dn         |10(1/0)  0(0/0) |           |np n nn
   (An)       |10(1/0)  4(1/0) |        nr |np n nn
   (An)+      |10(1/0)  4(1/0) |        nr |np n nn
   -(An)      |10(1/0)  6(1/0) |n       nr |np n nn
   (d16,An)   |10(1/0)  8(2/0) |     np nr |np n nn
   (d8,An,Xn) |10(1/0) 10(2/0) |n    np nr |np n nn
   (xxx).W    |10(1/0)  8(2/0) |     np nr |np n nn
   (xxx).L    |10(1/0) 12(3/0) |  np np nr |np n nn
   #<data>    |10(1/0)  4(1/0) |     np    |np n nn
trap :        |                |           |
 <ea>,Dn :    |                |           |
  .W :        |                |           |
   Dn > Src : |                |           |
    Dn        |38(5/3)  0(0/0) |           |np       nn ns ns nS nV nv nP  n nP
    (An)      |38(5/3)  4(1/0) |        nr |np       nn ns ns nS nV nv nP  n nP
    (An)+     |38(5/3)  4(1/0) |        nr |np       nn ns ns nS nV nv nP  n nP
    -(An)     |38(5/3)  6(1/0) |n       nr |np       nn ns ns nS nV nv nP  n nP
    (d16,An)  |38(5/3)  8(2/0) |     np nr |np       nn ns ns nS nV nv nP  n nP
    (d8,An,Xn)|38(5/3) 10(2/0) |n    np nr |np       nn ns ns nS nV nv nP  n nP
    (xxx).W   |38(5/3)  8(2/0) |     np nr |np       nn ns ns nS nV nv nP  n nP
    (xxx).L   |38(5/3) 12(3/0) |  np np nr |np       nn ns ns nS nV nv nP  n nP
    #<data>   |38(5/3)  4(1/0) |     np    |np       nn ns ns nS nV nv nP  n nP
   Dn < 0 :   |                |           |
    Dn        |40(5/3)  0(0/0) |           |np n     nn ns ns nS nV nv nP  n nP
    (An)      |40(5/3)  4(1/0) |        nr |np n     nn ns ns nS nV nv nP  n nP
    (An)+     |40(5/3)  4(1/0) |        nr |np n     nn ns ns nS nV nv nP  n nP
    -(An)     |40(5/3)  6(1/0) |n       nr |np n     nn ns ns nS nV nv nP  n nP
    (d16,An)  |40(5/3)  8(2/0) |     np nr |np n     nn ns ns nS nV nv nP  n nP
    (d8,An,Xn)|40(5/3) 10(2/0) |n    np nr |np n     nn ns ns nS nV nv nP  n nP
    (xxx).W   |40(5/3)  8(2/0) |     np nr |np n     nn ns ns nS nV nv nP  n nP
    (xxx).L   |40(5/3) 12(3/0) |  np np nr |np n     nn ns ns nS nV nv nP  n nP
    #<data>   |40(5/3)  4(1/0) |     np    |np n     nn ns ns nS nV nv nP  n nP
NOTES :
  . For more information about the "trap" cases, see Exception Processing.

[Note that the Exception Processing section lists those lone "n" cycles as n-
which I do not understand, so I will only note that there is a discrepancy.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        LEA       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
<ea>,An :         |                 |
  .L :            |                 |
    (An)          |  4(1/0)         |                               np
    (d16,An)      |  8(2/0)         |                          np   np
    (d8,An,Xn)    | 12(2/0)         |                        n np n np
    (xxx).W       |  8(2/0)         |                          np   np
    (xxx).L       | 12(3/0)         |                       np np   np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       JSR        |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
<ea> :            |                 |
    (An)          | 16(2/2)         |                      nP nS ns nP
    (d16,An)      | 18(2/2)         |                 n    nP nS ns nP
    (d8,An,Xn)    | 22(2/2)         |                 n nn nP nS ns nP
    (xxx).W       | 18(2/2)         |                 n    nP nS ns nP
    (xxx).L       | 20(3/2)         |                   np nP nS ns nP

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       JMP        |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
<ea> :            |                 |
    (An)          |  8(2/0)         |                      nP       nP
    (d16,An)      | 10(2/0)         |                 n    nP       nP
    (d8,An,Xn)    | 14(2/0)         |                 n nn nP       nP
    (xxx).W       | 10(2/0)         |                 n    nP       nP
    (xxx).L       | 12(3/0)         |                   np nP       nP
NOTES :
  .M68000UM probably has incorrect bus read accesses for the JMP (d8,An,Xn),Dn
   instruction. It reads "14(3/0)" which is contradicted by USP4325121.

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
     MOVE USP     |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
 An,USP :         |  4(1/0)         |                               np
 USP,An :         |  4(1/0)         |                               np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       RESET      |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
                  | 132(1/0)        |                      nn (??-)* np
NOTES :
  .(??-)* is for 124 cycles when the CPU will asserts the /RSTO signal in order
   to reset all external devices. Normally, the CPU won't use the bus during
   these cycles.
  .The RESET instruction has nothing to do with the /RESET exception.

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       NOP        |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
                  |  4(1/0)         |                               np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       STOP       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
                  |  4(0/0)         |                               nx
NOTES :
  .At this point, there are no real clues of how the second microcyle of this
   instruction is spent. [I annotated this with an 'x' but it seems obvious
   to me that the bus is idle. Refilling the pipeline would take at least
   8 cycles and would be a waste since the PC stops advancing.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
     RTE, RTR     |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
                  | 20(5/0)         |                      nU nu nu nP nP
NOTES :
  .M68000UM is probably wrong about bus read accesses for the RTR instruction.
   It reads "20(2/0)" but, according to USP4325121, and with a little common
   sense, 2 bus read accesses aren't enough for reading the status register
   and program counter values from the stack, not to mention prefetching.
   [The 68008 timing table also concurs. That's my go-to for checking typos.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       RTS        |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
                  | 16(4/0)         |                   nU nu    nP nP

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
      TRAPV       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
no trap           |  4(1/0)         |    np
   trap           | 34(5/3)         |    np             ns nS ns nV nv nP  n nP
NOTES :
  . For more information about the "trap" line, see Exception Processing.

[The trap timing and bus usage are inconsistent with CHK and other exceptions.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       LINK       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
An,#<data> :      |                 |
  .W :            | 16(2/2)         |                      np nS ns np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
      UNLNK       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
An :              | 12(3/0)         |                         nU nu np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
  ILLEGAL, TRAP   |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
                  | 34(4/3)         |             nn    ns ns nS nV nv nP  n nP
NOTES :
  .For more information about these instructions, see Exception Processing.




*******************************************************************************
  Line 0101
    ADDQ, DBcc, Scc, SUBQ
*******************************************************************************
-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
    ADDQ, SUBQ    |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
#<data>,<ea> :    |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    An            |  8(1/0)  0(0/0) |               |               np       nn
    (An)          |  8(1/1)  4(1/0) |            nr |               np nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np nw
  .L :            |                 |               |
    Dn            |  8(1/0)  0(0/0) |               |               np       nn
    An            |  8(1/0)  0(0/0) |               |               np       nn
    (An)          | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    (An)+         | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    -(An)         | 12(1/2) 10(2/0) | n       nR nr |               np nw nW
    (d16,An)      | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (d8,An,Xn)    | 12(1/2) 14(3/0) | n    np nR nr |               np nw nW
    (xxx).W       | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (xxx).L       | 12(1/2) 16(4/0) |   np np nR nr |               np nw nW
NOTES :
  .M68000UM is probably wrong for the instruction timing for ADDQ.W #<data>,An.
   It reads "4(1/0)" but, according to USP4325121, this instruction is based on
   the same microwords as ADDQ.L #<data>,Dn and ADDQ.L #<data>,An which have a
   "8(1/0)" timing. That makes sense because of the calculation of a 32 bit
   address on a 16-bit ALU. In addition, MC68000/AC and evaluation on real
   hardware confirm the 8-cycle timing. Furthermore, the corrected timing
   makes ADDQ and SUBQ consistent in terms of timing.

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       DBcc       |      INSTR      |                   INSTR
------------------+-----------------+------------------------------------------
Dn,<label> :      |                 |
  branch taken    | 10(2/0)         |                      n nP       nP
  branch not taken|                 |
    cc true       | 12(2/0)         |                      n     n np np
    counter exp   | 14(3/0)         |                      n nP    np np
NOTES :
  .DBcc does not exist in USP4325121, which only has a primitive DCNT
   instruction that never existed in production versions of the MC68000 CPU.
   Nevertheless, looking at the DCNT and Bcc micro/nanowords can lead to a
   realistic idea of how DBcc should work. At least, this re-engineering
   of DBcc matches the timings for this instruction as written in M68000UM.
FLOWCHART :
                   cc (no branch)      n                 /cc
                   +-------------------+-------------------+
                   n                             z (exp)   nP       /z (branch)
                   |                             +---------+---------+
                   +---------------------------->np                  |
                                                 |                   |
                                                 np                  nP

[I made some assumptions about np vs. nP necessitating tweaking the flowchart.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        Scc       |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea> :            |                 |               |
  .B :            |                 |               |
    cc false      |                 |               |
      Dn          |  4(1/0)  0(0/0) |               |               np
      (An)        |  8(1/1)  4(1/0) |            nr |               np    nw
      (An)+       |  8(1/1)  4(1/0) |            nr |               np    nw
      -(An)       |  8(1/1)  6(1/0) | n          nr |               np    nw
      (d16,An)    |  8(1/1)  8(2/0) |      np    nr |               np    nw
      (d8,An,Xn)  |  8(1/1) 10(2/0) | n    np    nr |               np    nw
      (xxx).W     |  8(1/1)  8(2/0) |      np    nr |               np    nw
      (xxx).L     |  8(1/1) 12(3/0) |   np np    nr |               np    nw
    cc true       |                 |               |
      Dn          |  6(1/0)  0(0/0) |               |               np       n
      (An)        |  8(1/1)  4(1/0) |            nr |               np    nw
      (An)+       |  8(1/1)  4(1/0) |            nr |               np    nw
      -(An)       |  8(1/1)  6(1/0) | n          nr |               np    nw
      (d16,An)    |  8(1/1)  8(2/0) |      np    nr |               np    nw
      (d8,An,Xn)  |  8(1/1) 10(2/0) | n    np    nr |               np    nw
      (xxx).W     |  8(1/1)  8(2/0) |      np    nr |               np    nw
      (xxx).L     |  8(1/1) 12(3/0) |   np np    nr |               np    nw




*******************************************************************************
  Line 0110
    Bcc, BRA, BSR
*******************************************************************************
-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        BRA       |      INSTR      |                   INSTR
------------------+-----------------+------------------------------------------
<label> :         |                 |
  .B, .S or .W :  | 10(2/0)         |                 n          nP nP

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        BSR       |      INSTR      |                   INSTR
------------------+-----------------+------------------------------------------
<label> :         |                 |
  .B .S or .W :   | 18(2/2)         |                 n    nS ns nP nP

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        Bcc       |      INSTR      |                   INSTR
------------------+-----------------+------------------------------------------
<label> :         |                 |
 .B or .S :       |                 |
  branch taken    | 10(2/0)         |                 n          nP nP
  branch not taken|  8(1/0)         |                nn             np
 .W :             |                 |
  branch taken    | 10(2/0)         |                 n          nP nP
  branch not taken| 12(2/0)         |                nn          np np




*******************************************************************************
  Line 0111
    MOVEQ
*******************************************************************************
-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       MOVEQ      |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
#<data>,Dn :      |                 |
  .L :            |  4(1/0)         |                               np




*******************************************************************************
  Line 1000                             &    Line 1100
    DIVS, DIVU, OR, SBCD                       ABCD, AND, EXG, MULS, MULU
*******************************************************************************
-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
    ABCD, SBCD    |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
Dy,Dx :           |                 |
  .B :            |  6(1/0)         |                               np       n
-(Ay),-(Ax) :     |                 |
  .B :            | 18(3/1)         |                 n    nr    nr np nw

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
      AND, OR     |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,Dn :         |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    (An)          |  4(1/0)  4(1/0) |            nr |               np
    (An)+         |  4(1/0)  4(1/0) |            nr |               np
    -(An)         |  4(1/0)  6(1/0) | n          nr |               np
    (d16,An)      |  4(1/0)  8(2/0) |      np    nr |               np
    (d8,An,Xn)    |  4(1/0) 10(2/0) | n    np    nr |               np
    (xxx).W       |  4(1/0)  8(2/0) |      np    nr |               np
    (xxx).L       |  4(1/0) 12(3/0) |   np np    nr |               np
    #<data>       |  4(1/0)  4(1/0) |      np       |               np
  .L :            |                 |               |
    Dn            |  8(1/0)  0(0/0) |               |               np       nn
    (An)          |  6(1/0)  8(2/0) |         nR nr |               np       n
    (An)+         |  6(1/0)  8(2/0) |         nR nr |               np       n
    -(An)         |  6(1/0) 10(2/0) | n       nR nr |               np       n
    (d16,An)      |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (d8,An,Xn)    |  6(1/0) 14(3/0) | n    np nR nr |               np       n
    (xxx).W       |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (xxx).L       |  6(1/0) 16(4/0) |   np np nR nr |               np       n
    #<data>       |  8(1/0)  8(2/0) |   np np       |               np       nn
Dn,<ea> :         |                 |               |
  .B or .W :      |                 |               |
    (An)          |  8(1/1)  4(1/0) |            nr |               np nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np nw
  .L :            |                 |               |
    (An)          | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    (An)+         | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    -(An)         | 12(1/2) 10(2/0) | n       nR nr |               np nw nW
    (d16,An)      | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (d8,An,Xn)    | 12(1/2) 14(3/0) | n    np nR nr |               np nw nW
    (xxx).W       | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (xxx).L       | 12(1/2) 16(4/0) |   np np nR nr |               np nw nW

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       DIVU       |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,Dn :        /                  |               |
  .W :          |                   |               |
    Dn          | 76+?(1/0)  0(0/0) |               | nn n [seq.] n nn np
    (An)        | 76+?(1/0)  4(1/0) |            nr | nn n [seq.] n nn np
    (An)+       | 76+?(1/0)  4(1/0) |            nr | nn n [seq.] n nn np
    -(An)       | 76+?(1/0)  6(1/0) | n          nr | nn n [seq.] n nn np
    (d16,An)    | 76+?(1/0)  8(2/0) |      np    nr | nn n [seq.] n nn np
    (d8,An,Xn)  | 76+?(1/0) 10(2/0) | n    np    nr | nn n [seq.] n nn np
    (xxx).W     | 76+?(1/0)  8(2/0) |      np    nr | nn n [seq.] n nn np
    (xxx).L     | 76+?(1/0) 12(3/0) |   np np    nr | nn n [seq.] n nn np
    #<data>     | 76+?(1/0)  4(1/0) |      np       | nn n [seq.] n nn np
NOTES :
  .Overflow always cost 10 cycles (n nn np).
  .For more information about division by zero, see Exception Processing.
  .[seq.] refers to 15 consecutive blocks to be chosen in the following 3 :
   (nn), (nnn-) or (nnn-n).
   (see following flowchart for details).
  .Best case : 76 cycles (nn n [nn]*15 n nn np)   [Way below what UM implies!]
  .Worst case : 136 (140 ?) cycles. [UM has 140 for the "maximum basic value"]
FLOWCHART :
                                       n
                                       n             Divide by zero
                  +--------------------+--------------------+
  Overflow        n                                         n
      +-----------+----------+                              n
     np                      n<---------------------+-+-+   ns
                             n                      | | |   ns
               No more bits  |  pMSB=0       pMSB=1 | | |   nS
                       +-----+-----+-----------+    | | |   nV
                       n    MSB=0  n- MSB=1    |    | | |   nV
                       np      +---+---+       +----+ | |   nP
                               |       n              | |   n
                               |       +--------------+ |   nP
                               +------------------------+
  .for each iteration of the loop : shift dividend to the left by 1 bit then
   subtract divisor to the MSW of new dividend, discard after test if result
   is negative keep it if positive.
  .MSB = most significant bit : bit at the far left of the dividend
  .pMSB = previous MSB : MSB used in the previous iteration of the loop

[If this algorithm is based on the patent then it might not be the algorithm
which was actually used, which could explain the discrepancy with the UM.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       DIVS       |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,Dn :       /                  /            /
 .W :         /                  /          /
  Dn        |120+?(1/0)  0(0/0)|          | nn nnn (n)n [seq] nnn-nnn n(n(n))np
  (An)      |120+?(1/0)  4(1/0)|        nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  (An)+     |120+?(1/0)  4(1/0)|        nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  -(An)     |120+?(1/0)  6(1/0)|n       nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  (d16,An)  |120+?(1/0)  8(2/0)|     np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  (d8,An,Xn)|120+?(1/0) 10(2/0)|n    np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  (xxx).W   |120+?(1/0)  8(2/0)|     np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  (xxx).L   |120+?(1/0) 12(3/0)|  np np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np
  #<data>   |120+?(1/0)  4(1/0)|     np   | nn nnn (n)n [seq] nnn-nnn n(n(n))np
NOTES :
  .Overflow cost 16 or 18 cycles depending on dividend sign (n nn nn (n)n np).
  .For more information about division by zero, see Exception Processing.
  .[seq.] refers to 15 consecutive blocks to be chosen in the following 2 :
   (nnn-n) or (nn-n).
   (see following flowchart for details).
  .Best case : 120-122 cycles depending on dividend sign. [Discrepancy with UM]
  .Worst case : 156 (158 ?) cycles. [UM has 158 for the "maximum basic value"]
FLOWCHART :
                                         n
                                         n                       Divide by zero
                                +--------+--------------------------------+
                                n                                         n
                                n                                         n
                  Dividend<0    n    Dividend>=0                          ns
                          +-----+-----+                                   ns
                          n           |                                   nS
                          +---------->n                                   nV
                                      |    Overflow                       nv
        +-----------------+      +----+----+                              nP
        | +----------+    +----->n         np                             n
        | |          +---------->n                                        nP
        | |                      n-
        | | MSB=1      MSB=0     n   No more bits
        | | +-----------+--------+--------+
        | +-+           |                 n
        +---------------+   divisor<0     n        divisor>0
                               +----------+-----------+
                               n         dividend<0   n   dividend>=0
                               n           +----------+----+
                               np          n               np
                                           n
                                           np
  .For each iteration of the loop : shift quotient to the left by 1 bit.
  .MSB = most significant bit : bit at the far left of the quotient.

[I changed > 0 to >= 0 for the dividend cases, which is purely my assumption.]

[If this algorithm is based on the patent then it might not be the algorithm
which was actually used, which could explain the discrepancy with the UM.]

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        EXG       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
  .L :            |                 |
    Dx,Dy         |  6(1/0)         |                               np       n
    Ax,Ay         |  6(1/0)         |                               np       n
    Dx,Ay         |  6(1/0)         |                               np       n

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
    MULU,MULS     |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,Dn :        /                  |               |
  .W :          /                   |               |
    Dn         | 38+2m(1/0)  0(0/0) |               |               np       n*
    (An)       | 38+2m(1/0)  4(1/0) |            nr |               np       n*
    (An)+      | 38+2m(1/0)  4(1/0) |            nr |               np       n*
    -(An)      | 38+2m(1/0)  6(1/0) | n          nr |               np       n*
    (d16,An)   | 38+2m(1/0)  8(2/0) |      np    nr |               np       n*
    (d8,An,Xn) | 38+2m(1/0) 10(2/0) | n    np    nr |               np       n*
    (xxx).W    | 38+2m(1/0)  8(2/0) |      np    nr |               np       n*
    (xxx).L    | 38+2m(1/0) 12(3/0) |   np np    nr |               np       n*
    #<data>    | 38+2m(1/0)  4(1/0) |      np       |               np       n*

NOTES :
  .for MULU 'm' = the number of binary ones in the source
    - Best case 38 cycles with $0
    - Worst case : 70 cycles with $FFFF
  .for MULS 'm' = concatenate the 16-bit pointed by <ea> with a zero as the LSB
   'm' is the resultant number of 10 or 01 patterns in the 17-bit source.
    - Best case : 38 cycles with $0 or $FFFF
    - Worst case : 70 cycles with $5555
  .in both cases : 'n*' should be replaced by 17+m consecutive 'n'
FLOWCHART :
                            np
         LSB=1              |           LSB=0
               +------------+------------+
               |                         |
            +->n------------------------>n<----+
            |                            |     | LSB=0 or
            |           No more bits     |     | 2LSB=00,11
   LSB=1 or +---------------+------------+-----+
   2LSB=01,10               |
                            n
  .  LSB =   least significant bit : the   bit  at the far right of the source.
  . 2LSB = 2 least significant bits: the 2 bits at the far right of the source.




*******************************************************************************
  Line 1001                             &    Line 1101
    SUB, SUBA, SUBX                            ADD, ADDA, ADDX
*******************************************************************************
-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
     ADD, SUB     |  INSTR     EA   | 1st Operand |  2nd OP (ea)  |   INSTR
------------------+-----------------+-------------+---------------+------------
<ea>,Dn :         |                 |              \              |
  .B or .W :      |                 |               |             |
    Dn            |  4(1/0)  0(0/0) |               |             | np
    An            |  4(1/0)  0(0/0) |               |             | np
    (An)          |  4(1/0)  4(1/0) |            nr |             | np
    (An)+         |  4(1/0)  4(1/0) |            nr |             | np
    -(An)         |  4(1/0)  6(1/0) | n          nr |             | np
    (d16,An)      |  4(1/0)  8(2/0) |      np    nr |             | np
    (d8,An,Xn)    |  4(1/0) 10(2/0) | n    np    nr |             | np
    (xxx).W       |  4(1/0)  8(2/0) |      np    nr |             | np
    (xxx).L       |  4(1/0) 12(3/0) |   np np    nr |             | np
    #<data>       |  4(1/0)  4(1/0) |      np       |             | np
  .L :            |                 |               |             |
    Dn            |  8(1/0)  0(0/0) |               |             | np       nn
    An            |  8(1/0)  0(0/0) |               |             | np       nn
    (An)          |  6(1/0)  8(2/0) |         nR nr |             | np       n
    (An)+         |  6(1/0)  8(2/0) |         nR nr |             | np       n
    -(An)         |  6(1/0) 10(2/0) | n       nR nr |             | np       n
    (d16,An)      |  6(1/0) 12(3/0) |      np nR nr |             | np       n
    (d8,An,Xn)    |  6(1/0) 14(3/0) | n    np nR nr |             | np       n
    (xxx).W       |  6(1/0) 12(3/0) |      np nR nr |             | np       n
    (xxx).L       |  6(1/0) 16(4/0) |   np np nR nr |             | np       n
    #<data>       |  8(1/0)  8(2/0) |   np np       |             | np       nn
Dn,<ea> :         |                 |              /              |
  .B or .W :      |                 |             |               |
    (An)          |  8(1/1)  4(1/0) |             |            nr | np nw
    (An)+         |  8(1/1)  4(1/0) |             |            nr | np nw
    -(An)         |  8(1/1)  6(1/0) |             | n          nr | np nw
    (d16,An)      |  8(1/1)  8(2/0) |             |      np    nr | np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) |             | n    np    nr | np nw
    (xxx).W       |  8(1/1)  8(2/0) |             |      np    nr | np nw
    (xxx).L       |  8(1/1) 12(3/0) |             |   np np    nr | np nw
  .L :            |                 |             |               |
    (An)          | 12(1/2)  8(2/0) |             |         nR nr | np nw nW
    (An)+         | 12(1/2)  8(2/0) |             |         nR nr | np nw nW
    -(An)         | 12(1/2) 10(2/0) |             | n       nR nr | np nw nW
    (d16,An)      | 12(1/2) 12(3/0) |             |      np nR nr | np nw nW
    (d8,An,Xn)    | 12(1/2) 14(3/0) |             | n    np nR nr | np nw nW
    (xxx).W       | 12(1/2) 12(3/0) |             |      np nR nr | np nw nW
    (xxx).L       | 12(1/2) 16(4/0) |             |   np np nR nr | np nw nW

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
    ADDA, SUBA    |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,An :         |                 |               |
  .B or .W :      |                 |               |
    Dn            |  8(1/0)  0(0/0) |               |               np       nn
    An            |  8(1/0)  0(0/0) |               |               np       nn
    (An)          |  8(1/0)  4(1/0) |            nr |               np       nn
    (An)+         |  8(1/0)  4(1/0) |            nr |               np       nn
    -(An)         |  8(1/0)  6(1/0) | n          nr |               np       nn
    (d16,An)      |  8(1/0)  8(2/0) |      np    nr |               np       nn
    (d8,An,Xn)    |  8(1/0) 10(2/0) | n    np    nr |               np       nn
    (xxx).W       |  8(1/0)  8(2/0) |      np    nr |               np       nn
    (xxx).L       |  8(1/0) 12(3/0) |   np np    nr |               np       nn
    #<data>       |  8(1/0)  4(1/0) |      np       |               np       nn
  .L :            |                 |               |
    Dn            |  8(1/0)  0(0/0) |               |               np       nn
    An            |  8(1/0)  0(0/0) |               |               np       nn
    (An)          |  6(1/0)  8(2/0) |         nR nr |               np       n
    (An)+         |  6(1/0)  8(2/0) |         nR nr |               np       n
    -(An)         |  6(1/0) 10(2/0) | n       nR nr |               np       n
    (d16,An)      |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (d8,An,Xn)    |  6(1/0) 14(3/0) | n    np nR nr |               np       n
    (xxx).W       |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (xxx).L       |  6(1/0) 16(4/0) |   np np nR nr |               np       n
    #<data>       |  8(1/0)  8(2/0) |   np np       |               np       nn

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
    ADDX, SUBX    |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
Dy,Dx :           |                 |
  .B or .W :      |  4(1/0)         |                               np
  .L :            |  8(1/0)         |                               np       nn
-(Ay),-(Ax) :     |                 |
  .B or .W :      | 18(3/1)         |              n nr    nr       np nw
  .L :            | 30(5/2)         |              n nr nR nr nR nw np    nW




*******************************************************************************
  Line 1010
    Reserved
*******************************************************************************

[I assume these have the same timings as Illegal Instruction exceptions.]




*******************************************************************************
  Line 1011
    CMP, CMPA, CMPM, EOR
*******************************************************************************
-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       CMP        |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,Dn :         |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    An            |  4(1/0)  0(0/0) |               |               np
    (An)          |  4(1/0)  4(1/0) |            nr |               np
    (An)+         |  4(1/0)  4(1/0) |            nr |               np
    -(An)         |  4(1/0)  6(1/0) | n          nr |               np
    (d16,An)      |  4(1/0)  8(2/0) |      np    nr |               np
    (d8,An,Xn)    |  4(1/0) 10(2/0) | n    np    nr |               np
    (xxx).W       |  4(1/0)  8(2/0) |      np    nr |               np
    (xxx).L       |  4(1/0) 12(3/0) |   np np    nr |               np
    #<data>       |  4(1/0)  4(1/0) |      np       |               np
  .L :            |                 |               |
    Dn            |  6(1/0)  0(0/0) |               |               np       n
    An            |  6(1/0)  0(0/0) |               |               np       n
    (An)          |  6(1/0)  8(2/0) |         nR nr |               np       n
    (An)+         |  6(1/0)  8(2/0) |         nR nr |               np       n
    -(An)         |  6(1/0) 10(2/0) | n       nR nr |               np       n
    (d16,An)      |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (d8,An,Xn)    |  6(1/0) 14(3/0) | n    np nR nr |               np       n
    (xxx).W       |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (xxx).L       |  6(1/0) 16(4/0) |   np np nR nr |               np       n
    #<data>       |  6(1/0)  8(2/0) |   np np       |               np       n

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       CMPA       |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
<ea>,An :         |                 |               |
  .B or .W :      |                 |               |
    Dn            |  6(1/0)  0(0/0) |               |               np       n
    An            |  6(1/0)  0(0/0) |               |               np       n
    (An)          |  6(1/0)  4(1/0) |            nr |               np       n
    (An)+         |  6(1/0)  4(1/0) |            nr |               np       n
    -(An)         |  6(1/0)  6(1/0) | n          nr |               np       n
    (d16,An)      |  6(1/0)  8(2/0) |      np    nr |               np       n
    (d8,An,Xn)    |  6(1/0) 10(2/0) | n    np    nr |               np       n
    (xxx).W       |  6(1/0)  8(2/0) |      np    nr |               np       n
    (xxx).L       |  6(1/0) 12(3/0) |   np np    nr |               np       n
    #<data>       |  6(1/0)  4(1/0) |      np       |               np       n
  .L :            |                 |               |
    Dn            |  6(1/0)  0(0/0) |               |               np       n
    An            |  6(1/0)  0(0/0) |               |               np       n
    (An)          |  6(1/0)  8(2/0) |         nR nr |               np       n
    (An)+         |  6(1/0)  8(2/0) |         nR nr |               np       n
    -(An)         |  6(1/0) 10(2/0) | n       nR nr |               np       n
    (d16,An)      |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (d8,An,Xn)    |  6(1/0) 14(3/0) | n    np nR nr |               np       n
    (xxx).W       |  6(1/0) 12(3/0) |      np nR nr |               np       n
    (xxx).L       |  6(1/0) 16(4/0) |   np np nR nr |               np       n
    #<data>       |  6(1/0)  8(2/0) |   np np       |               np       n

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       CMPM       |      INSTR      |                  INSTR
------------------+-----------------+------------------------------------------
(Ay)+,(Ax)+       |                 |
  .B or .W :      | 12(3/0)         |                      nr    nr np
  .L :            | 20(5/0)         |                   nR nr nR nr np

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
        EOR       |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
Dn,<ea> :         |                 |               |
  .B or .W :      |                 |               |
    Dn            |  4(1/0)  0(0/0) |               |               np
    (An)          |  8(1/1)  4(1/0) |            nr |               np nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np nw
  .L :            |                 |               |
    Dn            |  8(1/0)  0(0/0) |               |               np       nn
    (An)          | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    (An)+         | 12(1/2)  8(2/0) |         nR nr |               np nw nW
    -(An)         | 12(1/2) 10(2/0) | n       nR nr |               np nw nW
    (d16,An)      | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (d8,An,Xn)    | 12(1/2) 14(3/0) | n    np nR nr |               np nw nW
    (xxx).W       | 12(1/2) 12(3/0) |      np nR nr |               np nw nW
    (xxx).L       | 12(1/2) 16(4/0) |   np np nR nr |               np nw nW




*******************************************************************************
  Line 1110
    ASL, ASR, LSL, LSR, ROL, ROR, ROXL, ROXR
*******************************************************************************
-------------------------------------------------------------------------------
     ASL, ASR,    |    Exec Time    |               Data Bus Usage
     LSL, LSR,    |                 |
     ROL, ROR,    |                 |
    ROXL, ROXR    |  INSTR     EA   |  1st OP (ea)  |          INSTR
------------------+-----------------+---------------+--------------------------
Dx,Dy :           |                 |               |
  .B or .W :      |  6+2m(1/0)      |               |               np    n* n
  .L :            |  8+2m(1/0)      |               |               np    n* nn
#<data>,Dy :      |                 |               |
  .B or .W :      |  6+2m(1/0)      |               |               np    n  n*
  .L :            |  8+2m(1/0)      |               |               np    nn n*
<ea> :            |                 |               |
  .B or .W :      |                 |               |
    (An)          |  8(1/1)  4(1/0) |            nr |               np    nw
    (An)+         |  8(1/1)  4(1/0) |            nr |               np    nw
    -(An)         |  8(1/1)  6(1/0) | n          nr |               np    nw
    (d16,An)      |  8(1/1)  8(2/0) |      np    nr |               np    nw
    (d8,An,Xn)    |  8(1/1) 10(2/0) | n    np    nr |               np    nw
    (xxx).W       |  8(1/1)  8(2/0) |      np    nr |               np    nw
    (xxx).L       |  8(1/1) 12(3/0) |   np np    nr |               np    nw
NOTES :
  .'m' is the shift count.
  .'n*' should be replaced by 'm' consecutive 'n' characters.




*******************************************************************************
  Line 1111
    Reserved
*******************************************************************************

[I assume these have the same timings as Illegal Instruction exceptions.]




*******************************************************************************
                      EXCEPTION PROCESSING EXECUTION TIMES
*******************************************************************************
-------------------------------------------------------------------------------
                      | Periods  |               Data Bus Usage
----------------------+----------+---------------------------------------------
                      |          |
Group 0 :             |          |
  Address error       | 50(4/7)  |    nn ns ns nS ns ns ns nS nV nv nP  n nP
  Bus error           | 50(4/7)  |    nn ns ns nS ns ns ns nS nV nv nP  n nP
  /RESET              | 40(6/0)  |    (n-)*5   nn       nF nf nV nv nP  n nP
Group 1 :             |          |
  Trace               | 34(4/3)  |             nn    ns nS ns nV nv nP  n nP
  Interrupt           | 44(5/3)  |     n nn ns ni n-  n nS ns nV nv nP  n nP
  Privilege Violation | 34(4/3)  |             nn    ns ns nS nV nv nP  n nP
  Illegal Instruction | 34(4/3)  |             nn    ns ns nS nV nv nP  n nP
Group 2 :             |          |
  CHK Instruction     |*40(5/3)+ |    np (n-)  nn    ns ns nS nV nv nP  n nP
  Divide by Zero      | 38(4/3)+ |          nn nn    ns ns nS nV nv nP  n nP
  TRAP instruction    | 34(4/3)  |             nn    ns ns nS nV nv nP  n nP
  TRAPV instruction   | 34(5/3)  |    np             ns nS ns nV nv nP  n nP

* CHK exceptions are 38 or 40 cycles long. Refer to the CHK instruction.

NOTES:
  .For CHK and Divide by Zero, you must add effective address calculation time
   to the period (according to the respective instruction descriptions above).
  .For CHK, Divide by Zero, Illegal, TRAP and TRAPV :
    .The number of clock periods for the "trap" lines, include the times for
     all stacking, the vector fetch, and fetching the first two words of the
     exception handler routine. [<- referring to the instruction descriptions]
    .First to be pushed on the stack is the program counter low word (at SP-2)
     and the status register (at SP-6) then, finally, the program counter high
     word (at SP-4).
  ./RESET above indicates the time from when /RESET and /HALT are first sampled
   as negated to when instruction execution starts. For a subsequent external
   reset, asserting these signals for 10 clock cycles or longer is mandatory
   to initiate the reset sequence. During these 10 clock cycles, the CPU is
   in a halted state. However, an external reset signal that is asserted while
   the CPU is executing a reset instruction is ignored. Since the processor
   asserts the /RESET signal for 124 clock cycles during execution of a reset
   instruction, an external reset should assert /RESET for at least 132 clock
   periods.

[I changed CHK from 40(4/3)+ (which is what the UM says) to 40(5/3)+ which is
what the Bus Usage recorded above implies. Not sure about the (n-) though.]

[I've never been able to come up with a plausible explanation for why TRAPV
is (supposedly) 34 cycles instead of 38 despite having an extra read cycle
as compared to illegal-instruction exceptions. If "34" isn't an error in the
documentation then could someone please explain the discrepancy? And I don't
accept "np takes the place of the usual nn" as an answer because that conflicts
with how CHK exceptions work. I don't know if the bus usage is correct anyway.]




*******************************************************************************
                                   HALTED STATE
*******************************************************************************
-------------------------------------------------------------------------------
                      | Periods  |               Data Bus Usage
----------------------+----------+---------------------------------------------
                      |  ?(0/0)  |  (n-)*
NOTES :
  .This state is entered when a major failure happens and can only be exited by
   resetting the CPU. Between these two events fit as many (n-) as necessary.
